Sinangil, M., Lin, Y., Liao, H. und Chang, J. (2019) „A 290-m V, 7-nm Ultra-Low-Voltage One-Port SRAM Compiler Design Using a 12 T Write Contention and Read Upset Free Bit-Cell“, IEEE Journal of Solid-State Circuits, Solid-State Circuits, IEEE Journal of, IEEE J. Solid-State Circuits, 54(4), S. 1152-1160. doi:10.1109/JSSC.2019.2895236.
Chicago Manual of Style 17th edition (full note)Sinangil, M.E., Y. Lin, H. Liao, und J. Chang. „A 290-MV, 7-Nm Ultra-Low-Voltage One-Port SRAM Compiler Design Using a 12 T Write Contention and Read Upset Free Bit-Cell“. IEEE Journal of Solid-State Circuits, Solid-State Circuits, IEEE Journal Of, IEEE J. Solid-State Circuits 54, Nr. 4 (1. April 2019): 1152-60. https://doi.org/10.1109/JSSC.2019.2895236.
American Psychological Association 7th editionSinangil, M., Lin, Y., Liao, H., & Chang, J. (2019). A 290-m V, 7-nm Ultra-Low-Voltage One-Port SRAM Compiler Design Using a 12 T Write Contention and Read Upset Free Bit-Cell. IEEE Journal of Solid-State Circuits, Solid-State Circuits, IEEE Journal Of, IEEE J. Solid-State Circuits, 54(4), 1152-1160. https://doi.org/10.1109/JSSC.2019.2895236
Modern Language Association 9th editionSinangil, M., Y. Lin, H. Liao, und J. Chang. „A 290-MV, 7-Nm Ultra-Low-Voltage One-Port SRAM Compiler Design Using a 12 T Write Contention and Read Upset Free Bit-Cell“. IEEE Journal of Solid-State Circuits, Solid-State Circuits, IEEE Journal Of, IEEE J. Solid-State Circuits, Bd. 54, Nr. 4, April 2019, S. 1152-60, https://doi.org/10.1109/JSSC.2019.2895236.
ISO-690 (author-date, Deutsch)SINANGIL, M.E., Y. LIN, H. LIAO und J. CHANG, 2019. A 290-m V, 7-nm Ultra-Low-Voltage One-Port SRAM Compiler Design Using a 12 T Write Contention and Read Upset Free Bit-Cell. IEEE Journal of Solid-State Circuits, Solid-State Circuits, IEEE Journal of, IEEE J. Solid-State Circuits. 1 April 2019. Bd. 54, Nr. 4, S. 1152-1160. DOI 10.1109/JSSC.2019.2895236