Cite Them Right 11th edition - Harvard

Yershov, R.D. (2018) „A Scalable VHDL-Implementation Technique of the Priority Encoder Structure into FPGA“, in. doi:10.1109/ELNANO.2018.8477465.

Chicago Manual of Style 17th edition (full note)

Yershov, Roman D. „A Scalable VHDL-Implementation Technique of the Priority Encoder Structure into FPGA“. In . https://doi.org/10.1109/ELNANO.2018.8477465.

American Psychological Association 7th edition

Yershov, R. D. (2018, April 1). A Scalable VHDL-Implementation Technique of the Priority Encoder Structure into FPGA. https://doi.org/10.1109/ELNANO.2018.8477465

Modern Language Association 9th edition

Yershov, R. D. A Scalable VHDL-Implementation Technique of the Priority Encoder Structure into FPGA. 2018, https://doi.org/10.1109/ELNANO.2018.8477465.

ISO-690 (author-date, Deutsch)

YERSHOV, Roman D., 2018. A Scalable VHDL-Implementation Technique of the Priority Encoder Structure into FPGA. In: . 1 April 2018

Achtung: Diese Zitate sind unter Umständen nicht zu 100% korrekt.