Lee, Y., Waterman, A., Cook, H., Zimmer, B., Keller, B., Puggelli, A., Kwak, J., Jevtic, R., Bailey, S., Blagojevic, M., Chiu, P.-F., Avizienis, R., Richards, B., Bachrach, J., Patterson, D., Alon, E., Nikolic, B. und Asanovic, K. (2016) „An Agile Approach to Building RISC-V Microprocessors“, IEEE Micro, Micro, IEEE, 36(2), S. 8-20. doi:10.1109/MM.2016.11.

Lee, Yunsup, Andrew Waterman, Henry Cook, Brian Zimmer, Ben Keller, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Stevo Bailey, Milovan Blagojevic, Pi-Feng Chiu, Rimas Avizienis, Brian Richards, Jonathan Bachrach, David Patterson, Elad Alon, Bora Nikolic, und Krste Asanovic. „An Agile Approach to Building RISC-V Microprocessors“. IEEE Micro, Micro, IEEE 36, Nr. 2 (1. März 2016): 8-20. https://doi.org/10.1109/MM.2016.11.

Lee, Y., Waterman, A., Cook, H., Zimmer, B., Keller, B., Puggelli, A., Kwak, J., Jevtic, R., Bailey, S., Blagojevic, M., Chiu, P.-F., Avizienis, R., Richards, B., Bachrach, J., Patterson, D., Alon, E., Nikolic, B., & Asanovic, K. (2016). An Agile Approach to Building RISC-V Microprocessors. IEEE Micro, Micro, IEEE, 36(2), 8-20. https://doi.org/10.1109/MM.2016.11

Lee, Y., A. Waterman, H. Cook, B. Zimmer, B. Keller, A. Puggelli, J. Kwak, R. Jevtic, S. Bailey, M. Blagojevic, P.-F. Chiu, R. Avizienis, B. Richards, J. Bachrach, D. Patterson, E. Alon, B. Nikolic, und K. Asanovic. „An Agile Approach to Building RISC-V Microprocessors“. IEEE Micro, Micro, IEEE, Bd. 36, Nr. 2, März 2016, S. 8-20, https://doi.org/10.1109/MM.2016.11.

LEE, Yunsup, Andrew WATERMAN, Henry COOK, Brian ZIMMER, Ben KELLER, Alberto PUGGELLI, Jaehwa KWAK, Ruzica JEVTIC, Stevo BAILEY, Milovan BLAGOJEVIC, Pi-Feng CHIU, Rimas AVIZIENIS, Brian RICHARDS, Jonathan BACHRACH, David PATTERSON, Elad ALON, Bora NIKOLIC und Krste ASANOVIC, 2016. An Agile Approach to Building RISC-V Microprocessors. IEEE Micro, Micro, IEEE. 1 März 2016. Bd. 36, Nr. 2, S. 8-20. DOI 10.1109/MM.2016.11