B, A.K.D., Bairwa, B., Vamsidath, B., V, U., P, T. und Rao, T. (2023) „HDL Programming and Sequential Circuitry for Multi-Core RISC-V Processor“, in. doi:10.1109/ICSSES58299.2023.10201166.
Chicago Manual of Style 17th edition (full note)B, Anil Kumar D, Bansilal Bairwa, Bhadriraju Vamsidath, Ujwal V, Tharun P, und Tushaar Rao. „HDL Programming and Sequential Circuitry for Multi-Core RISC-V Processor“. In . https://doi.org/10.1109/ICSSES58299.2023.10201166.
American Psychological Association 7th editionB, A. K. D., Bairwa, B., Vamsidath, B., V, U., P, T., & Rao, T. (2023, Juli 7). HDL Programming and Sequential Circuitry for Multi-Core RISC-V Processor. https://doi.org/10.1109/ICSSES58299.2023.10201166
Modern Language Association 9th editionB, A. K. D., B. Bairwa, B. Vamsidath, U. V, T. P, und T. Rao. HDL Programming and Sequential Circuitry for Multi-Core RISC-V Processor. 2023, https://doi.org/10.1109/ICSSES58299.2023.10201166.
ISO-690 (author-date, Deutsch)B, Anil Kumar D, Bansilal BAIRWA, Bhadriraju VAMSIDATH, Ujwal V, Tharun P und Tushaar RAO, 2023. HDL Programming and Sequential Circuitry for Multi-Core RISC-V Processor. In: . 7 Juli 2023