Treffer: Hierarchical Model Checking of SystemVerilog-Specified Asynchronous Circuits for Deadlock Detection

Title:
Hierarchical Model Checking of SystemVerilog-Specified Asynchronous Circuits for Deadlock Detection
Authors:
Lu, L., Pan, M., Lu, Y., Li, X.
Source:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on. 44(6):2424-2437 Jun, 2025
Database:
IEEE Xplore Digital Library