Treffer: and K Steiglitz: A VLSI layout for a pipe-lined dadda multiplier

Title:
and K Steiglitz: A VLSI layout for a pipe-lined dadda multiplier
Authors:
Peter R. Cappello, Kenneth Steiglitz
Contributors:
The Pennsylvania State University CiteSeerX Archives
Source:
http://www.cs.princeton.edu/~ken/dadda83.pdf.
Publication Year:
1983
Collection:
CiteSeerX
Subject Terms:
Categories and Subject Descriptors, B.2.1 [Arithmetic and Logic Structures, Design Styles-parallel, pipeline, C.5.4 [Computer System Implementation, VLSI Systems General Terms, Algorithms, Design, Performance Additional Key Words and Phrases, multiplier, VLSI, layout, complexity
Document Type:
Fachzeitschrift text
File Description:
application/pdf
Language:
English
Relation:
http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.433.9428; http://www.cs.princeton.edu/~ken/dadda83.pdf
Availability:
http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.433.9428
http://www.cs.princeton.edu/~ken/dadda83.pdf
Rights:
Metadata may be used without restrictions as long as the oai identifier remains attached to it.
Accession Number:
edsbas.DA9E83C9
Database:
BASE

Weitere Informationen

Parallel counters (unary-to-binary converters) are the principal component of a Dadda multiplier. We specify a design first for a pipelined parallel counter, and then for a complete multiplier. As a result of its structural regularity, the layout is suitable for use in a VLSI implementation. We analyze the complexity of the resulting design using a VLSI model of computation, showing that it is optimal with respect to both its period and latency. In this sense the design compares favorably with other recent VLSI multiplier designs.