Treffer: Grain Morphology Effects on Void Formation and Electromigration-Induced Failure in Copper Interconnects.

Electromigration, driven by increasing current densities in scaled integrated circuits, poses a serious reliability challenge in semiconductor manufacturing, often culminating in void formation and interconnect failure. As interconnect dimensions shrink to the nanoscale, the influence of microstructural features and grain morphology on interconnect reliability and degradation mechanisms becomes increasingly significant. In this work, we develop a physics-based phase field model to investigate the void formation and evolution in copper interconnects subjected to electromigration. Our simulations closely align with experimental trends, revealing that voids predominantly emerge at or initiate from the cathode end, with their evolution strongly influenced by grain morphology. In the surface diffusion-limited scenario (SDLS), grain boundaries significantly promote void formation, resulting in increased void sizes. Under the grain boundary diffusion-limited scenario (GBDLS), void nucleation in bamboo structure (BS) and polycrystalline structure (PS) interconnects occurs relatively early, often initiating near the interface between the copper and the capping layer. The voltage distribution exhibits noticeable inhomogeneity, with high electric field intensities localized at grain boundaries and void surfaces. The electromigration-induced mass flux predominantly flows from the bottom right toward the left. Additionally, an increased number of copper grains leads to larger voids, with a more pronounced effect in the SDLS. Furthermore, electromigration-induced void growth progressively reduces electrical conductivity. These findings elucidate the complex interplay between grain morphology, electromigration-driven void formation, and electrical performance degradation in copper interconnects, and are anticipated to offer valuable insights into microstructure-dependent failure mechanisms while supporting process optimization in advanced interconnect fabrication. [ABSTRACT FROM AUTHOR]

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