Treffer: Unified Approach for Parallel Prefix Adders Description.

Some of the most important architectures of parallel prefix adder are described by an unified formalism and compared in terms of speed/area trade off. The aim is not to improve the fastest adder, but instead to give a method to balance complexity and speed. By mixing different styles, the lowest cost for an imposed delay can be achieved. The result from VLSI design student project, using this approach is also briefly discussed. [ABSTRACT FROM AUTHOR]